Electronic packaging of the IBM System z196 enterprise-class server processor cage

the IBM System z196 enterprise-class server processor cage T. Strach F. Bosco K. L. Christian K. R. Covi M. Eckert G. R. Edlund R. Frech H. Harrer A. Huber D. Kaller M. Kindscher A. Z. Muszynski G. A. Peterson C. Siviero J. Supper O. A. Torreiter T.-M. Winkel In this paper, we describe the firstand second-level system packaging structure of the IBM zEnterpriseA 196 (z196) enterprise-class server. The design point required a more than 50% overall increase in system performance (in millions of instructions per second) in comparison to its predecessor. This resulted in a new system design that includes, among other things, increased input/output bandwidth, more processors with higher frequencies, and increased current demand of more than 2,000 A for the six processor chips and two cache chips per multichip module. To achieve these targets, we implemented several new packaging technologies. The z196 enterprise-class server uses a new differential memory interface between the processor chips and custom-designed server memory modules. The electrical power delivery system design follows a substantially new approach using Vicor Factor PowerA blocks, which results in higher packaging integration density and minimized package electrical losses. The power noise decoupling strategy was changed because of the availability of deep-trench technology on the new processor chip generation.